It is desirable for memory flash devices with NOR-architecture to be able to complete the erase operations with sufficiently fast timing. Normally, these devices use the Fowler-Nordheim Tunneling to perform the erase operations. With this methodology, high voltages are applied contemporaneously to the memory cells to be erased. The erase operation then completes by discharging these high voltages to ground. However, there is a trade-off between the speed and the reliability of the erase operation. To obtain a proper balance between the two, voltages in the order of 7 to 9V for the positive voltage, and −8 to −10V for the negative voltage, are typically used. Two techniques are available for the positive voltage: a positive voltage is applied only to the bulk node; or a positive voltage is applied to the bulk node and to the source node of the memory cells. In this specification, only the second method is analyzed but either technique can be applied.
FIG. 1 illustrates a simplified physical and electrical model to represent the conventional erase phases performed on a sector of a memory device. The electrical model is composed of three capacitors: Cggnd 101, Cgb 102, and Cbgnd 103. Cgb 102 represents the gate-bulk capacitor, which has a capacitance equal to the total gate capacitance of the sector to be erased versus the common cell bulk-source node. The top plate of Cgb 102 represents the common gate node 104, and the bottom plate represents the bulk-source node 105. Cggnd 101 represents the capacitance of the gate node 104 versus all other nodes except the bulk-source node 105 (Node 1), and Cbgnd 103 represents the capacitance of the bulk-source node 105 versus all other nodes except the gate node 104 (Node 2). Fowler-Nordheim Tunneling erase is performed by applying a negative voltage on the gate node 104 and a positive voltage on the bulk-source node 105. With the voltages above, the total voltage seen by Cgb 102 is in the order of approximately 20V.
Since the capacitance value of all gates is relatively high, by capacitive coupling, the gate node 104 (starting from −8/−10V) can reach a high negative voltage during bulk-source discharge. Moreover, the bulk-source node 105 can reach a high positive voltage during gate discharge in the same way. This value is very dangerous for all internal MOS devices which can tolerate, normally, a voltage difference no higher than 11V. After 11V, serious reliability problems occur. Thus, it's very important to control these discharge phases after the erase operations with special circuitry to anticipate reliability problems.
FIG. 2 illustrates one conventional approach for preventing reliability problems caused by reached voltage exiting from erase operations. Here, the top plate and bottom plate of Cbg 202 are coupled together via the initial discharge circuit 204 before discharging the gate node 104 and the bulk-source node 105 to ground. FIG. 2 also includes a digital control circuit 205 that completes the discharge operation by connecting to ground the gate node 104 and the bulk-source node 105. The discharge operation is controlled because the gate node voltage variation cannot be lower than the initial voltage, and the bulk-source voltage variation cannot be higher than the initial voltage. For example, if Cggnd=Cbgnd and the start absolute voltage is the same for the gate node 104 and the bulk-source node 105, the Cgb plates will be discharged to the same value of zero.
In the case with Cggnd>>>Cbgnd or Cggnd<<<Cbgnd, the node with a bigger capacitance versus all other nodes will tend to keep the initial voltage value while the other voltage node will decrease its value quickly. The positive and negative voltages will have their absolute values reduced without dangerous drop or overshoot. The gate and source/bulk voltages will go to ground without dangerous oscillations.
However, with this approach, the initial discharge circuit 204 is required to work between −8/−10V (gate voltage) and 7/9V (bulk-source voltage). This requires a complicated design, where voltage limitators may be necessary in order for the circuit to work with initial voltages near 20V.
Accordingly, there exists a need for an improved method for high voltage discharge phase after an erase pulse in a flash memory device. The improved method should address reliability concerns due to the high voltage without complicated designs or voltage limitators, while also providing a fast discharge time after erase operations. The present invention addresses such a need.